Embodiments of the present invention relate to semiconductor processing, and more particularly to analyzing wafers for defects or other deviations.
Semiconductor devices are manufactured in a fabrication facility (fab) by executing a number of processes on lots of wafers running through various tools and equipment of the fab. These various tools and equipment are used to perform depositions, photolithography, implantations, and metallizations among many other steps in forming semiconductor devices. Because of the small size associated with advanced technology nodes, even very small defects on a wafer can cause a failure of a die (i.e., corresponding to a semiconductor device) of the wafer.
Various engineers and others involved in the semiconductor manufacturing process are interested in improving yields associated with semiconductor manufacture, and various efforts are put forth to increase the number of dies on a wafer that are defect free. To this end, various tools are available to perform inspection and review of wafers during the manufacturing process. For example, an inspection tool may be used to perform various inspections of the wafers of a wafer lot to identify defects present after a given manufacturing step. In some fabs, some or all wafers of a wafer lot are inspected in an inspection tool at the conclusion of one or more manufacturing steps. In some cases, one or more of the inspected wafers may then be provided to a review tool for further review, e.g., by way of imaging to obtain image data that can later be analyzed by an engineer. Often, a random selection of wafers for review in a review tool is performed.
Historically, the number of wafers that are inspected for defects is greater than the number of wafers that are reviewed. Due to this arrangement, there may be a loss of learning, as some of the wafers that were not reviewed may contain defect patterns of interest for yield learning purposes. If an interesting defect pattern is appearing in wafer lots, an engineer may specify that one or more wafers having a certain number of defects should be reviewed in a review tool. Accordingly, a technician or other fab employee must manually parse the inspection data to identify such wafers and provide them to the review tool, which is a time-consuming process.
Furthermore, it may often occur that after a wafer is inspected and reviewed a defect reduction engineer or other fab employee may find an interesting defect pattern on one or more wafers that were inspected in the inspection tool but not reviewed. Because by the time of this analysis, the wafer lot may have passed along to further operations in the fab, the engineer may not be able to send the lot back to the review tool to improve yield learning by capturing review tool information regarding the defects. Accordingly, a potentially valuable source of information to attempt to resolve a root cause of defects is lost, and one or more additional lots may be exposed to the defect issue.